Defect analysis and a new fault model for multi-port SRAMs

Pradeep Nagaraj; Shambhu Upadhyaya; Kamran Zarrineh; Dean Adams

doi:10.1109/DFTVS.2001.966790

Defect analysis and a new fault model for multi-port SRAMs

Pradeep Nagaraj
, Shambhu Upadhyaya
, Kamran Zarrineh
, Dean Adams

Department of Computer Science and Engineering

Qualcomm Incorporated
DFT Architecture
Global Foundries, Inc.

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

Semiconductor memory failures depend on the behavior of its components. This paper deals with testing of defects occurring in the memory cells of a multi-port memory. We also consider the resistive shorts between word/bit lines of same and different ports of the memory. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of patterns. Not only have existing models been taken into account in our simulation but also a new fault model for the multi-port memory is introduced. The boundaries of failure for the proposed defects are identified. ũ 2001 IEEE.

Original language	English
Pages (from-to)	366-374
Number of pages	9
Journal	IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
DOIs	https://doi.org/10.1109/DFTVS.2001.966790
State	Published - 2001

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10.1109/DFTVS.2001.966790

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@article{c7af9ed1f33e48d0be9c094bc4b3d4d8,

title = "Defect analysis and a new fault model for multi-port SRAMs",

abstract = "Semiconductor memory failures depend on the behavior of its components. This paper deals with testing of defects occurring in the memory cells of a multi-port memory. We also consider the resistive shorts between word/bit lines of same and different ports of the memory. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of patterns. Not only have existing models been taken into account in our simulation but also a new fault model for the multi-port memory is introduced. The boundaries of failure for the proposed defects are identified. ũ 2001 IEEE.",

author = "Pradeep Nagaraj and Shambhu Upadhyaya and Kamran Zarrineh and Dean Adams",

year = "2001",

doi = "10.1109/DFTVS.2001.966790",

language = "English",

pages = "366--374",

journal = "IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems",

issn = "1063-6722",

}

TY - JOUR

T1 - Defect analysis and a new fault model for multi-port SRAMs

AU - Nagaraj, Pradeep

AU - Upadhyaya, Shambhu

AU - Zarrineh, Kamran

AU - Adams, Dean

PY - 2001

Y1 - 2001

N2 - Semiconductor memory failures depend on the behavior of its components. This paper deals with testing of defects occurring in the memory cells of a multi-port memory. We also consider the resistive shorts between word/bit lines of same and different ports of the memory. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of patterns. Not only have existing models been taken into account in our simulation but also a new fault model for the multi-port memory is introduced. The boundaries of failure for the proposed defects are identified. ũ 2001 IEEE.

AB - Semiconductor memory failures depend on the behavior of its components. This paper deals with testing of defects occurring in the memory cells of a multi-port memory. We also consider the resistive shorts between word/bit lines of same and different ports of the memory. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of patterns. Not only have existing models been taken into account in our simulation but also a new fault model for the multi-port memory is introduced. The boundaries of failure for the proposed defects are identified. ũ 2001 IEEE.

UR - https://www.scopus.com/pages/publications/0035193951

U2 - 10.1109/DFTVS.2001.966790

DO - 10.1109/DFTVS.2001.966790

M3 - Article

AN - SCOPUS:0035193951

SN - 1063-6722

SP - 366

EP - 374

JO - IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

JF - IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

ER -

Defect analysis and a new fault model for multi-port SRAMs

Abstract

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