Cost model analysis of DFT based fault tolerant SOC designs

A lot of emphasis has been placed on the test cost of chips and a variety of models have been proposed in the literature. However, they do not include the fault tolerance consideration. Existing models are incomplete with the fact that most do not take into account the costs involved once the chip reaches the market. This paper addresses these limitations by introducing the cost model for a fault tolerant system taking into account the reliability factor of a system. This model will help designers analyze the need for a fault tolerant system and its feasibility in the industry. This paper models the costs involved during the life cycle of a chip. Two case studies using the proposed model are presented in order to substantiate the need to put fault tolerant designs into chips.