Abstract
In this paper, we present a complexity reduced turbo decoding method by using concatenated error detection codes with the turbo codes. First, a large data frame for turbo encoding is divided into multiple small packets followed by cyclic redundancy check (CRC) parity bits. The essential idea is to fully utilize the interim CRC detection results inside the turbo decoding. Trellis constraints will be exploited to redesign the turbo decoding algorithms so that a large reduction in computational complexity as well as an excellent decoding performance can be achieved. Exprimental results over the constrained log-MAP algorithm is provided. However, the idea proposed in the research is generic to any trellis-related decoding algorithms when the decoder has the knowledge that some of bits have been correctly decoded. Furthermore, the error localization feature provided by this method is also important to applications such as source data post-processing and Hybrid-ARQ.
| Original language | English |
|---|---|
| Pages (from-to) | 678-681 |
| Number of pages | 4 |
| Journal | IEEE Vehicular Technology Conference |
| Volume | 58 |
| Issue number | 1 |
| State | Published - 2003 |
| Event | 2003 IEEE 58th Vehicular Technology Conference, VTC2003-Fall - Orlando, FL, United States Duration: Oct 6 2003 → Oct 9 2003 |
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