Comparison of Real-Valued FFT Architectures for Low-Throughput Applications using FPGA

While many Fast Fourier Transform (FFT) architectures have been presented for computing real-valued FFT (RFFT), which of these architectures is best suited for low-throughput applications such as biomedical signals which are typically sampled between 256 Hz and 1 kHz remains unclear. This paper implements and compares throughput, resources, and energy consumption of three different hardware architectures for real-valued FFT algorithms using Xilinx Zynq-7000 FPGA. The RFFT architectures exploit the conjugate symmetry property of the real signals, thereby eliminating about half of the computations compared to a complex FFT. The three FFT architectures investigated in this paper include: single processing element (SPE), pipelined, and in-place. It is shown that, for a 256-point RFFT, using FPGA, the in-place architectures require the least device resources when compared to the pipelined architectures, while the throughput of the pipelined architectures is approximately 8 times that of the in-place architecture.