Comparison of power consumption among asynchronous design styles with their synchronous counterparts

Seokjin Kim; Ramalingam Sridhar

Comparison of power consumption among asynchronous design styles with their synchronous counterparts

Seokjin Kim
, Ramalingam Sridhar

Department of Computer Science and Engineering

SUNY Buffalo

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

This paper presents a power consumption comparison of synchronous and asynchronous standard cell implementations. The comparison is made with a simple data path block, a 4-bit serial parallel multiplier and the components used in the blocks. To provide a common basis of comparison, the standard cell design method is used with a suite of EDA tools for layout synthesis. Average power consumption is simulated using Spice3 with a power meter. The results of the simulation are tabulated and the advantages and disadvantages of each design are discussed.

Original language	English
Pages	7-10
Number of pages	4
State	Published - 1994
Event	Proceedings of the 37th Midwest Symposium on Circuits and Systems. Part 2 (of 2) - Lafayette, LA, USA Duration: Aug 3 1994 → Aug 5 1994

Conference

Conference	Proceedings of the 37th Midwest Symposium on Circuits and Systems. Part 2 (of 2)
City	Lafayette, LA, USA
Period	08/3/94 → 08/5/94

Cite this

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title = "Comparison of power consumption among asynchronous design styles with their synchronous counterparts",

abstract = "This paper presents a power consumption comparison of synchronous and asynchronous standard cell implementations. The comparison is made with a simple data path block, a 4-bit serial parallel multiplier and the components used in the blocks. To provide a common basis of comparison, the standard cell design method is used with a suite of EDA tools for layout synthesis. Average power consumption is simulated using Spice3 with a power meter. The results of the simulation are tabulated and the advantages and disadvantages of each design are discussed.",

author = "Seokjin Kim and Ramalingam Sridhar",

year = "1994",

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note = "Proceedings of the 37th Midwest Symposium on Circuits and Systems. Part 2 (of 2) ; Conference date: 03-08-1994 Through 05-08-1994",

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AU - Kim, Seokjin

AU - Sridhar, Ramalingam

PY - 1994

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N2 - This paper presents a power consumption comparison of synchronous and asynchronous standard cell implementations. The comparison is made with a simple data path block, a 4-bit serial parallel multiplier and the components used in the blocks. To provide a common basis of comparison, the standard cell design method is used with a suite of EDA tools for layout synthesis. Average power consumption is simulated using Spice3 with a power meter. The results of the simulation are tabulated and the advantages and disadvantages of each design are discussed.

AB - This paper presents a power consumption comparison of synchronous and asynchronous standard cell implementations. The comparison is made with a simple data path block, a 4-bit serial parallel multiplier and the components used in the blocks. To provide a common basis of comparison, the standard cell design method is used with a suite of EDA tools for layout synthesis. Average power consumption is simulated using Spice3 with a power meter. The results of the simulation are tabulated and the advantages and disadvantages of each design are discussed.

UR - https://www.scopus.com/pages/publications/0028744749

M3 - Paper

AN - SCOPUS:0028744749

SP - 7

EP - 10

T2 - Proceedings of the 37th Midwest Symposium on Circuits and Systems. Part 2 (of 2)

Y2 - 3 August 1994 through 5 August 1994

ER -

Comparison of power consumption among asynchronous design styles with their synchronous counterparts

Abstract

Conference

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