CMOS wave pipelining using transmission-gate logic

A design method using CMOS Transmission-Gate Logic is presented for wave-pipelined circuits implementation. The basic circuits, referred to as Wave-pipelined Transmission-Gate Logic (WTGL), have complementary outputs driven by separate inverters. Timing analysis and simulation of the basic logic circuits demonstrate that delay variations for all input pattern combinations are considerably reduced. Most importantly, the basic circuits can implement various logic functions with gate delays of the same magnitude. Practical circuits are designed and they verify the advantages of WTGL technique.