TY - GEN
T1 - Clocking and synchronization in sub-90nm System-on-Chip (SoC) designs
AU - Sridhar, Ramalingam
PY - 2004
Y1 - 2004
N2 - The techniques of clocking and synchronization in sub-90nm System-on-Chip (SoC) designs are presented. The design of an efficient clock distribution network and synchronization circuitry dictates proper functioning of the SoC, and to ensure seamless integration and operation of SoCs, different IPs have to be properly clocked and synchronized with one another. Popular synchronization techniques of the IPs such as mesochronous clocking and plesiochronous clocking, and other schemes such as pausable clocking can be used. Different clock distribution schemes, such as, symmetric H tree, X tree, and buffered clock tree schemes used to minimize skew.
AB - The techniques of clocking and synchronization in sub-90nm System-on-Chip (SoC) designs are presented. The design of an efficient clock distribution network and synchronization circuitry dictates proper functioning of the SoC, and to ensure seamless integration and operation of SoCs, different IPs have to be properly clocked and synchronized with one another. Popular synchronization techniques of the IPs such as mesochronous clocking and plesiochronous clocking, and other schemes such as pausable clocking can be used. Different clock distribution schemes, such as, symmetric H tree, X tree, and buffered clock tree schemes used to minimize skew.
UR - https://www.scopus.com/pages/publications/16244389634
M3 - Conference contribution
AN - SCOPUS:16244389634
SN - 0780387139
SN - 9780780387133
T3 - Proceedings of the 2004 IEEE Dallas/CAS Workshop: Implementation of High Performance Circuits. DCAS-04
SP - 49
EP - 84
BT - Proceedings of the 2004 IEEE Dallas/CAS Workshop
T2 - Proceedings of the 2004 IEEE Dallas/CAS Workshop: Implementation of High Performance Circuits. DCAS-04
Y2 - 27 September 2004 through 27 September 2004
ER -