Clock-biased local bit line for high performance register files

A clock-biased local bit line (CB-LBL) scheme is presented to achieve high access speed and energy efficient operation for register files. Simulation results in 32nm high-k/metal gate CMOS predictive technology show 49.5% read latency reduction and 39.4% power savings, with less than 5% impact on noise immunity and within 1% increase in area overhead. Additionally, CB-LBL can achieve 99.8% parametric yield compared to its original 47.6% (conventional LBL design), while being scalable.