@inproceedings{46794bca271b4467adc02e83cacf6a08,
title = "Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology",
abstract = "This paper presents a lifetime simulator for both Front-End-of-Line (FEOL) time dependent dielectric breakdown (TDDB) and the newly emerging Middle-of-Line (MOL) time dependent dielectric breakdown for FinFET technology. A lifetime assessment flow for digital circuits and microprocessors is proposed for the target wearout mechanisms, and its associated vulnerable feature extraction algorithms are discussed in detail. Our simulator incorporates the detailed electrical stress, temperature, linewidth of each standard cell within the digital circuit and microprocessor. Also, FEOL TDDB and MOL TDDB lifetimes are combined in the calculation of TDDB lifetime. Circuit designers can use the resulting lifetime information to guide and improve their circuits to make them more robust and reliable.",
keywords = "digital circuit, frontend-of-line dielectric breakdown, lifetime simulator, microprocessor, middle-of-line breakdown, reliability, time-dependent dielectric breakdown, wearout",
author = "Kexin Yang and Taizhi Liu and Rui Zhang and Linda Milor",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 36th IEEE VLSI Test Symposium, VTS 2018 ; Conference date: 22-04-2018 Through 25-04-2018",
year = "2018",
month = may,
day = "29",
doi = "10.1109/VTS.2018.8368651",
language = "English",
series = "Proceedings of the IEEE VLSI Test Symposium",
publisher = "IEEE Computer Society",
pages = "1--6",
booktitle = "Proceedings - 2018 IEEE 36th VLSI Test Symposium, VTS 2018",
address = "United States",
}