CEE-Gr: A global router with performance optimization under multi-constraints

Ling Zhang; Tong Jing; Xianlong Hong; Jingyu Xu; Jinjun Xiong; Lei He

CEE-Gr: A global router with performance optimization under multi-constraints

Ling Zhang
, Tong Jing
, Xianlong Hong
, Jingyu Xu
, Jinjun Xiong
, Lei He

Department of Computer Science and Engineering

Tsinghua University
University of California at Los Angeles

Research output: Contribution to journal › Article › peer-review

Abstract

A global routing algorithm with performance optimization under multi-constraints is proposed, which studies RLC coupling noise, timing performance, and routability simultaneously at global routing level. The algorithm is implemented and the global router is called CEE-Gr. The CEE-Gr is tested on MCNC benchmarks and the experimental results are promising.

Original language	English
Pages (from-to)	508-515
Number of pages	8
Journal	Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors
Volume	25
Issue number	5
State	Published - May 2004

Keywords

Global routing
Multi-constraints
Performance optimization
Physical design
VLSI/ULSI

Cite this

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title = "CEE-Gr: A global router with performance optimization under multi-constraints",

abstract = "A global routing algorithm with performance optimization under multi-constraints is proposed, which studies RLC coupling noise, timing performance, and routability simultaneously at global routing level. The algorithm is implemented and the global router is called CEE-Gr. The CEE-Gr is tested on MCNC benchmarks and the experimental results are promising.",

keywords = "Global routing, Multi-constraints, Performance optimization, Physical design, VLSI/ULSI",

author = "Ling Zhang and Tong Jing and Xianlong Hong and Jingyu Xu and Jinjun Xiong and Lei He",

year = "2004",

month = may,

language = "English",

volume = "25",

pages = "508--515",

journal = "Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors",

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publisher = "Kexue Chubaneshe/Science Press",

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TY - JOUR

T1 - CEE-Gr

T2 - A global router with performance optimization under multi-constraints

AU - Zhang, Ling

AU - Jing, Tong

AU - Hong, Xianlong

AU - Xu, Jingyu

AU - Xiong, Jinjun

AU - He, Lei

PY - 2004/5

Y1 - 2004/5

N2 - A global routing algorithm with performance optimization under multi-constraints is proposed, which studies RLC coupling noise, timing performance, and routability simultaneously at global routing level. The algorithm is implemented and the global router is called CEE-Gr. The CEE-Gr is tested on MCNC benchmarks and the experimental results are promising.

AB - A global routing algorithm with performance optimization under multi-constraints is proposed, which studies RLC coupling noise, timing performance, and routability simultaneously at global routing level. The algorithm is implemented and the global router is called CEE-Gr. The CEE-Gr is tested on MCNC benchmarks and the experimental results are promising.

KW - Global routing

KW - Multi-constraints

KW - Performance optimization

KW - Physical design

KW - VLSI/ULSI

UR - https://www.scopus.com/pages/publications/7944238697

M3 - Article

AN - SCOPUS:7944238697

SN - 0253-4177

VL - 25

SP - 508

EP - 515

JO - Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

JF - Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

IS - 5

ER -

CEE-Gr: A global router with performance optimization under multi-constraints

Abstract

Keywords

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