BUILT-IN SELF TESTING PLA DESIGN WITH HIGH FAULT COVERAGE.

Kewal K. Saluja; Shambhu J. Upadhyaya

BUILT-IN SELF TESTING PLA DESIGN WITH HIGH FAULT COVERAGE.

Kewal K. Saluja
, Shambhu J. Upadhyaya

Department of Computer Science and Engineering

University of Wisconsin-Madison

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A method of designing built-in self-testing (BIST) PLAs is proposed in which the test pattern generator and response evaluator circuits are very simple and consist only of shift registers and counters. The extra hardware in the BIST PLA mainly appears in the form of additional lines in the AND and/or OR planes. The new design requires a reorganization of the AND and OR planes on the basis of the number of crosspoints in the product and output lines, respectively. The fault coverage is higher than that of any known BIST techniques. The design presented is simple and can easily be incorporated into existing design automation systems.

Original language	English
Title of host publication	Unknown Host Publication Title
Publisher	IEEE
Pages	596-599
Number of pages	4
ISBN (Print)	0818607351
State	Published - 1986

Cite this

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title = "BUILT-IN SELF TESTING PLA DESIGN WITH HIGH FAULT COVERAGE.",

abstract = "A method of designing built-in self-testing (BIST) PLAs is proposed in which the test pattern generator and response evaluator circuits are very simple and consist only of shift registers and counters. The extra hardware in the BIST PLA mainly appears in the form of additional lines in the AND and/or OR planes. The new design requires a reorganization of the AND and OR planes on the basis of the number of crosspoints in the product and output lines, respectively. The fault coverage is higher than that of any known BIST techniques. The design presented is simple and can easily be incorporated into existing design automation systems.",

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AU - Saluja, Kewal K.

AU - Upadhyaya, Shambhu J.

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N2 - A method of designing built-in self-testing (BIST) PLAs is proposed in which the test pattern generator and response evaluator circuits are very simple and consist only of shift registers and counters. The extra hardware in the BIST PLA mainly appears in the form of additional lines in the AND and/or OR planes. The new design requires a reorganization of the AND and OR planes on the basis of the number of crosspoints in the product and output lines, respectively. The fault coverage is higher than that of any known BIST techniques. The design presented is simple and can easily be incorporated into existing design automation systems.

AB - A method of designing built-in self-testing (BIST) PLAs is proposed in which the test pattern generator and response evaluator circuits are very simple and consist only of shift registers and counters. The extra hardware in the BIST PLA mainly appears in the form of additional lines in the AND and/or OR planes. The new design requires a reorganization of the AND and OR planes on the basis of the number of crosspoints in the product and output lines, respectively. The fault coverage is higher than that of any known BIST techniques. The design presented is simple and can easily be incorporated into existing design automation systems.

UR - https://www.scopus.com/pages/publications/0022953937

M3 - Conference contribution

AN - SCOPUS:0022953937

SN - 0818607351

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EP - 599

BT - Unknown Host Publication Title

PB - IEEE

ER -

BUILT-IN SELF TESTING PLA DESIGN WITH HIGH FAULT COVERAGE.

Abstract

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