Buffered single-phase clocked logic for high-speed CMOS pipelined circuits

This paper presents a pseudo single-phase clocked CMOS dynamic logic style called Buffered Single-phase Clocked (BSPC) logic for high-speed pipelined circuits. The use of buffered straight-line clock distribution methods eliminates the need for the slow P-type transistors in the true single-phase clocking (TSPC) logic. Thus further speed improvement of TSPC has been achieved while maintaining the advantages of using a single-phase clock. The clocking constraints are described. An 8-b adder with reverse clock distribution has been designed in a 0.5-μm CMOS technology which operates at a clock rate of up to 1.33 GHz.