TY - GEN
T1 - BIST PLAs, pass or fail--A case study
AU - Upadhyaya, Shambhu J.
AU - Thodiyil, John A.
PY - 1990
Y1 - 1990
N2 - Numerous built-in self-testing (BIST) designs exist for the testing of programmable logic arrays (PLA), but their practical usefulness has not been studied. Several BIST designs were implemented and compared using a common methodology of implementation. A yield analysis is performed to characterize the yield degradation due to the BIST design methodology. Preliminary findings of this work are that the BIST approach results in considerable degradation of yield, and therefore may not be suitable as a test vehicle for PLAs.
AB - Numerous built-in self-testing (BIST) designs exist for the testing of programmable logic arrays (PLA), but their practical usefulness has not been studied. Several BIST designs were implemented and compared using a common methodology of implementation. A yield analysis is performed to characterize the yield degradation due to the BIST design methodology. Preliminary findings of this work are that the BIST approach results in considerable degradation of yield, and therefore may not be suitable as a test vehicle for PLAs.
UR - https://www.scopus.com/pages/publications/0025541310
U2 - 10.1145/123186.123452
DO - 10.1145/123186.123452
M3 - Conference contribution
AN - SCOPUS:0025541310
SN - 081869650X
T3 - 27th ACM/IEEE Design Automation Conference. Proceedings 1990
SP - 724
EP - 727
BT - 27th ACM/IEEE Design Automation Conference. Proceedings 1990
PB - Publ by IEEE
T2 - 27th ACM/IEEE Design Automation Conference
Y2 - 24 June 1990 through 28 June 1990
ER -