Area and power efficient mismatched filters based on sidelobe inversion

A computationally efficient mismatched filter comprised of a matched filter in cascade with a multi-stage filter based on sidelobe inversion is proposed. For this approach to work, the given code has to satisfy certain conditions as derived in this work. For the proposed filter to be of practical significance, the given autocorrelation must have a computationally efficient representation including the case of sparse and/or small integer valued sidelobes such as in Barker codes. When implemented in VLSI, significantly smaller chip area and less power are required compared to the length-optimal filters achieving comparable sidelobe suppression.