Analytical approach to fine tuning in CMOS wave-pipelining

Dipankar Talukdar; Ramalingam Sridhar

Analytical approach to fine tuning in CMOS wave-pipelining

Dipankar Talukdar
, Ramalingam Sridhar

Department of Computer Science and Engineering

SUNY Buffalo

Research output: Contribution to journal › Conference article › peer-review

4 Scopus citations

Abstract

Fine tuning is an integral part of a wave-pipelined design process to achieve maximum clock speed. In this paper we present analytical approaches to two main components of the fine tuning process for CMOS designs, the computation of effective load capacitance at gate outputs and the transistor sizing of the driving gates to achieve equal rise and fall delay. Comparisons with Spice simulation results are presented to show the accuracy of the proposed approach.

Original language	English
Pages (from-to)	205-208
Number of pages	4
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
State	Published - 1996
Event	Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA Duration: Sep 23 1996 → Sep 27 1996

Cite this

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title = "Analytical approach to fine tuning in CMOS wave-pipelining",

abstract = "Fine tuning is an integral part of a wave-pipelined design process to achieve maximum clock speed. In this paper we present analytical approaches to two main components of the fine tuning process for CMOS designs, the computation of effective load capacitance at gate outputs and the transistor sizing of the driving gates to achieve equal rise and fall delay. Comparisons with Spice simulation results are presented to show the accuracy of the proposed approach.",

author = "Dipankar Talukdar and Ramalingam Sridhar",

year = "1996",

language = "English",

pages = "205--208",

journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

issn = "1063-0988",

note = "Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit ; Conference date: 23-09-1996 Through 27-09-1996",

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TY - JOUR

T1 - Analytical approach to fine tuning in CMOS wave-pipelining

AU - Talukdar, Dipankar

AU - Sridhar, Ramalingam

PY - 1996

Y1 - 1996

N2 - Fine tuning is an integral part of a wave-pipelined design process to achieve maximum clock speed. In this paper we present analytical approaches to two main components of the fine tuning process for CMOS designs, the computation of effective load capacitance at gate outputs and the transistor sizing of the driving gates to achieve equal rise and fall delay. Comparisons with Spice simulation results are presented to show the accuracy of the proposed approach.

AB - Fine tuning is an integral part of a wave-pipelined design process to achieve maximum clock speed. In this paper we present analytical approaches to two main components of the fine tuning process for CMOS designs, the computation of effective load capacitance at gate outputs and the transistor sizing of the driving gates to achieve equal rise and fall delay. Comparisons with Spice simulation results are presented to show the accuracy of the proposed approach.

UR - https://www.scopus.com/pages/publications/0029726878

M3 - Conference article

AN - SCOPUS:0029726878

SN - 1063-0988

SP - 205

EP - 208

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

T2 - Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit

Y2 - 23 September 1996 through 27 September 1996

ER -

Analytical approach to fine tuning in CMOS wave-pipelining

Abstract

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