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Analysis of multi-layered microelectronic packaging under uniformly distributed loading

  • SUNY Buffalo

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

An accurate estimate of interfacial stresses in multi-layered microelectronic packaging is very important for design and prediction of delamination-related failures. An analytical model for stress analysis of multi-layered stacks, which is based on an extension of Valisetty's model (Bending of Beams, Plates and Laminates: Refined Theories and Comparative Studies, Ph.D. thesis, Georgia Institute of Technology, Atlanta, March 1983), is proposed in this paper. This analytical approach considers each layer as a beam-type plate with orthotropic material properties. A new miniature material testing unit is developed. High sensitive Moiré interferometry was used to measure the strain field in the bi-material interfaces. The test data is in good agreement with the proposed analytical solution. The problem is also analyzed by a finite element analysis. Comparison of all three results indicates that the analytical procedure is far superior to finite element analysis for this problem.

Original languageEnglish
Pages (from-to)3331-3345
Number of pages15
JournalInternational Journal of Solids and Structures
Volume40
Issue number13-14
DOIs
StatePublished - 2003

Keywords

  • Interfacial delamination
  • Interfacial stress
  • Microelectronic packaging
  • Moiré interferometry
  • Multi-layered structure

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