Skip to main navigation Skip to search Skip to main content

Analysis of a fault tolerant scheme for processor ensembles

  • SUNY Buffalo

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The authors present and analyze a locally redundant (LR) scheme, applicable to a number of interconnection topologies, for designing fault tolerant processor ensembles. A switching structure is presented for reconfiguration, and it is shown that the LR scheme is area-efficient. A model for static analysis (yield) that takes into account processor, switch, and link failures is presented. This dynamic analysis, based on Markov models, includes the determination of operational availability of the fault tolerant system with and without graceful degradation. Closed-form expressions are also obtained for the transition probabilities of the Markov models in terms of the system parameters.

Original languageEnglish
Title of host publicationProceedings of the Hawaii International Conference on System Science
EditorsLee W. Hoevel, Bruce D. Shriver, Jay F.Jr. Nunamaker, Ralph H.Jr. Sprague, Velijko Milutinovic
PublisherPubl by Western Periodicals Co
Pages101-110
Number of pages10
ISBN (Print)0818620080
StatePublished - 1990
EventProceedings of the Twenty-Third Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track - Kailua-Kona, HI, USA
Duration: Jan 2 1990Jan 5 1990

Publication series

NameProceedings of the Hawaii International Conference on System Science
Volume1
ISSN (Print)0073-1129

Conference

ConferenceProceedings of the Twenty-Third Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track
CityKailua-Kona, HI, USA
Period01/2/9001/5/90

Fingerprint

Dive into the research topics of 'Analysis of a fault tolerant scheme for processor ensembles'. Together they form a unique fingerprint.

Cite this