Analysis and Design of Single Reference Reduced Summer Loading-Based Switched Capacitor DFE

Nevin Alex Jacob; Bibhudatta Sahoo

doi:10.1007/s00034-017-0664-9

Analysis and Design of Single Reference Reduced Summer Loading-Based Switched Capacitor DFE

Nevin Alex Jacob
, Bibhudatta Sahoo

Department of Electrical Engineering

Amrita Vishwa Vidyapeetham

Research output: Contribution to journal › Article › peer-review

Abstract

Decision feedback equalizers (DFE) are an integral part of modern serial link receivers. Attenuation in wireline communication channels causes pulse spreading. Hence, multi-tap post-cursor cancellation is necessary for reliable recovery of data at the receiver. However, the addition of multiple taps causes loading on the analog summing node which degrades the bandwidth of operation. This paper explores the design parameters of a switched capacitor-based DFE for multi-tap post-cursor cancellation with reduced summer loading. The architecture is validated by post-layout simulations done in UMC65SP technology. A PRBS-7 generator is used, and test cases are simulated upto 4.0 Gbps for two different channel attenuations around 20 dB.

Original language	English
Pages (from-to)	4994-5018
Number of pages	25
Journal	Circuits, Systems, and Signal Processing
Volume	36
Issue number	12
DOIs	https://doi.org/10.1007/s00034-017-0664-9
State	Published - Dec 1 2017

Keywords

Decision feedback equalizer (DFE)
Equalization
Finite impulse response (FIR)
Inter-symbol interference (ISI)
Serializer–deserializer (SerDes)
Switched capacitor (SC)
Unit interval (UI)

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10.1007/s00034-017-0664-9

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title = "Analysis and Design of Single Reference Reduced Summer Loading-Based Switched Capacitor DFE",

abstract = "Decision feedback equalizers (DFE) are an integral part of modern serial link receivers. Attenuation in wireline communication channels causes pulse spreading. Hence, multi-tap post-cursor cancellation is necessary for reliable recovery of data at the receiver. However, the addition of multiple taps causes loading on the analog summing node which degrades the bandwidth of operation. This paper explores the design parameters of a switched capacitor-based DFE for multi-tap post-cursor cancellation with reduced summer loading. The architecture is validated by post-layout simulations done in UMC65SP technology. A PRBS-7 generator is used, and test cases are simulated upto 4.0 Gbps for two different channel attenuations around 20 dB.",

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AB - Decision feedback equalizers (DFE) are an integral part of modern serial link receivers. Attenuation in wireline communication channels causes pulse spreading. Hence, multi-tap post-cursor cancellation is necessary for reliable recovery of data at the receiver. However, the addition of multiple taps causes loading on the analog summing node which degrades the bandwidth of operation. This paper explores the design parameters of a switched capacitor-based DFE for multi-tap post-cursor cancellation with reduced summer loading. The architecture is validated by post-layout simulations done in UMC65SP technology. A PRBS-7 generator is used, and test cases are simulated upto 4.0 Gbps for two different channel attenuations around 20 dB.

KW - Decision feedback equalizer (DFE)

KW - Equalization

KW - Finite impulse response (FIR)

KW - Inter-symbol interference (ISI)

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KW - Switched capacitor (SC)

KW - Unit interval (UI)

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Analysis and Design of Single Reference Reduced Summer Loading-Based Switched Capacitor DFE

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