TY - GEN
T1 - An efficient method for chip-level statistical capacitance extraction considering process variations with spatial correlation
AU - Zhang, Wangyang
AU - Yu, Wenjian
AU - Wang, Zeyi
AU - Yu, Zhiping
AU - Jiang, Rong
AU - Xiong, Jinjun
PY - 2008
Y1 - 2008
N2 - An efficient method is proposed to consider the process variations with spatial correlation, for chip-level capacitance extraction based on the window technique. In each window, an efficient technique of Hermite polynomial collocation (HPC) is presented to extract the statistical capacitance. The capacitance covariances between windows are then calculated to reflect the spatial correlation. The proposed method is practical for chip-level extraction task, and the experiments on full-path extraction exhibit its high accuracy and efficiency.
AB - An efficient method is proposed to consider the process variations with spatial correlation, for chip-level capacitance extraction based on the window technique. In each window, an efficient technique of Hermite polynomial collocation (HPC) is presented to extract the statistical capacitance. The capacitance covariances between windows are then calculated to reflect the spatial correlation. The proposed method is practical for chip-level extraction task, and the experiments on full-path extraction exhibit its high accuracy and efficiency.
UR - https://www.scopus.com/pages/publications/49749119482
U2 - 10.1109/DATE.2008.4484739
DO - 10.1109/DATE.2008.4484739
M3 - Conference contribution
AN - SCOPUS:49749119482
SN - 9783981080
SN - 9789783981089
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 580
EP - 585
BT - Design, Automation and Test in Europe, DATE 2008
T2 - Design, Automation and Test in Europe, DATE 2008
Y2 - 10 March 2008 through 14 March 2008
ER -