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An area-efficient VLSI implementation for programmable FIR filters based on a parameterized divide and conquer approach

  • T. Poonnen
  • , A. T. Fam
  • SUNY Buffalo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In this paper, we propose an optimal VLSI implementation for a class of programmable FIR filters with binary coefficients, whose architecture is based on a parameterized divide and conquer approach. The proposed design is shown to be easily extendable to FIR filters with multibit coefficients with arbitrary sign. The area efficiency achieved in comparison to direct form realization is demonstrated by VLSI implementation examples, synthesized in TSMC 0.18 micrometer single poly six metal layer CMOS process using state-of-art VLSI EDA tools. A control algorithm to configure the proposed implementation scheme is discussed.

Original languageEnglish
Title of host publicationProceedings of the 15th International Conference on Microelectronics, ICM 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages93-96
Number of pages4
ISBN (Electronic)9770520101
DOIs
StatePublished - 2003
Event15th International Conference on Microelectronics, ICM 2003 - Cairo, Egypt
Duration: Dec 9 2003 → Dec 11 2003

Publication series

NameProceedings of the International Conference on Microelectronics, ICM
Volume2003-January

Conference

Conference15th International Conference on Microelectronics, ICM 2003
Country/TerritoryEgypt
CityCairo
Period12/9/03 → 12/11/03

Keywords

  • CMOS process
  • Computer architecture
  • Electronic design automation and methodology
  • Field programmable gate arrays
  • Finite impulse response filter
  • Multicast algorithms
  • Optimal control
  • Switches
  • Transfer functions
  • Very large scale integration

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