An 8-bit Split CDAC-Based Noise-Shaping SAR ADC in 180 nm CMOS for Power Efficient Digitization of Sensor Signals

Noise shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) can achieve high resolution with low power consumption without the need to incorporate power-hungry transconductance amplifiers. An improved NS architecture is proposed that takes only one extra clock cycle for NS and achieves a first-order NS with a zero at 0.9 using an 8-bit split capacitor digital-to-analog converter (DAC) and passive capacitors for integration. The proposed architecture is implemented in 180 nm 1P6M CMOS process and achieves an signal-to-noise+distortion ratio (SNDR) of 69 dB with an effective-number-of-bits (ENOBs) of 11.16 occupying an active area of 0.07