An 8 Bit 4 GS/s 120 mW CMOS ADC

Hegong Wei; Peng Zhang; Bibhu Datta Sahoo; Behzad Razavi

doi:10.1109/JSSC.2014.2313571

An 8 Bit 4 GS/s 120 mW CMOS ADC

Hegong Wei
, Peng Zhang
, Bibhu Datta Sahoo
, Behzad Razavi

Department of Electrical Engineering

University of California at Los Angeles
Tsinghua University
Marvell Semiconductor, Ltd.

Research output: Contribution to journal › Article › peer-review

137 Scopus citations

Abstract

A time-interleaved ADC employs four pipelined time-interleaved channels along with a new timing mismatch detection algorithm and a high-resolution variable delay line. The digital background calibration technique suppresses the interchannel timing mismatches, achieving an SNDR of 44.4 dB and a figure of merit of 219 fJ/conversion-step in 65 nm CMOS technology.

Original language	English
Article number	6784501
Pages (from-to)	1751-1761
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	49
Issue number	8
DOIs	https://doi.org/10.1109/JSSC.2014.2313571
State	Published - Aug 2014

Keywords

Analog-to-digital conversion
interleaving
pipelined analog-to-digital converter (ADC)
time error detection and correction
timing calibration
variable delay lines

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10.1109/JSSC.2014.2313571

Cite this

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KW - interleaving

KW - pipelined analog-to-digital converter (ADC)

KW - time error detection and correction

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KW - variable delay lines

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An 8 Bit 4 GS/s 120 mW CMOS ADC

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Keywords

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