@inproceedings{71819b60c2bf4e2ea10e12a8203b6930,
title = "An 8-Bit 4-GS/s 120-mW CMOS ADC",
abstract = "A four-channel time-interleaved pipelined ADC employs a new timing calibration technique to suppress mismatch-induced spurs and achieve a Nyquist-rate SNDR of 44.4 dB. Designed in 65-nm CMOS technology, the ADC draws 120 mW, providing an FOM of 219 fJ per conversion step.",
author = "Hegong Wei and Peng Zhang and \{Datta Sahoo\}, Bibhu and Behzad Razavi",
year = "2013",
month = nov,
day = "7",
doi = "10.1109/CICC.2013.6658420",
language = "English",
isbn = "9781467361460",
series = "Proceedings of the Custom Integrated Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013",
address = "United States",
note = "35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 ; Conference date: 22-09-2013 Through 25-09-2013",
}