A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application

T. Rahul; Bibhudatta Sahoo; S. Arya; S. J. Parvathy; Veeresh Babu Vulligaddala

doi:10.1109/VLSID.2015.51

A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application

T. Rahul
, Bibhudatta Sahoo
, S. Arya
, S. J. Parvathy
, Veeresh Babu Vulligaddala

Department of Electrical Engineering

Amrita Vishwa Vidyapeetham
Ams Semiconductors India Pvt. Ltd

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper proposes a wide dynamic-range low-power signal conditioning circuit for low-side current sensing application. The proposed architecture uses a double sampling technique for switched capacitor programmable gain amplifier (SC-PGA) thus enabling the PGA to work at low frequency. However, the analog-to-digital converter (ADC), which digitizes the amplified signal works at high frequency to achieve high dynamic range. The double sampling technique relaxes the slew rate and settling requirement of the op amp in the PGA. The switched capacitor implementation obviates the need for explicit level-shifting circuit while enabling rail-to-rail input common mode. The closed loop SC-PGA architecture is very robust to gain drift due to temperature and supply voltage variation. The design incorporates correlated double sampling technique to overcome offset and flicker noise. The analog-to-digital converter used in this design is a multi-bit second order ΔΣ-ADC [14]. The circuit is implemented in AMS 0.35 μm CMOS process with 3.3 V supply. Simulations show that the overall system, i.e., PGA and ΔΣ-ADC, achieves a dynamic range in excess of 80 dB while consuming 2 mA.

Original language	English
Title of host publication	Proceedings of the 28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems
Publisher	IEEE Computer Society
Pages	265-270
Number of pages	6
Edition	February
ISBN (Electronic)	9781479966585
DOIs	https://doi.org/10.1109/VLSID.2015.51
State	Published - Feb 4 2015
Event	28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems - Bangalore, India Duration: Jan 3 2015 → Jan 7 2015

Publication series

Name	Proceedings of the IEEE International Conference on VLSI Design
Number	February
Volume	2015-February
ISSN (Print)	1063-9667

Conference

Conference	28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems
Country/Territory	India
City	Bangalore
Period	01/3/15 → 01/7/15

Keywords

double sampling
Low-side current sensing
PGA
second-order ΔΣADC

Access to Document

10.1109/VLSID.2015.51

Cite this

Rahul, T., Sahoo, B., Arya, S., Parvathy, S. J., & Vulligaddala, V. B. (2015). A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application. In Proceedings of the 28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems (February ed., pp. 265-270). Article 7031744 (Proceedings of the IEEE International Conference on VLSI Design; Vol. 2015-February, No. February). IEEE Computer Society. https://doi.org/10.1109/VLSID.2015.51

Rahul, T. ; Sahoo, Bibhudatta ; Arya, S. et al. / A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application. Proceedings of the 28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems. February. ed. IEEE Computer Society, 2015. pp. 265-270 (Proceedings of the IEEE International Conference on VLSI Design; February).

@inproceedings{88e059ca00c644418490f5933d392cf2,

title = "A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application",

abstract = "This paper proposes a wide dynamic-range low-power signal conditioning circuit for low-side current sensing application. The proposed architecture uses a double sampling technique for switched capacitor programmable gain amplifier (SC-PGA) thus enabling the PGA to work at low frequency. However, the analog-to-digital converter (ADC), which digitizes the amplified signal works at high frequency to achieve high dynamic range. The double sampling technique relaxes the slew rate and settling requirement of the op amp in the PGA. The switched capacitor implementation obviates the need for explicit level-shifting circuit while enabling rail-to-rail input common mode. The closed loop SC-PGA architecture is very robust to gain drift due to temperature and supply voltage variation. The design incorporates correlated double sampling technique to overcome offset and flicker noise. The analog-to-digital converter used in this design is a multi-bit second order ΔΣ-ADC [14]. The circuit is implemented in AMS 0.35 μm CMOS process with 3.3 V supply. Simulations show that the overall system, i.e., PGA and ΔΣ-ADC, achieves a dynamic range in excess of 80 dB while consuming 2 mA.",

keywords = "double sampling, Low-side current sensing, PGA, second-order ΔΣADC",

author = "T. Rahul and Bibhudatta Sahoo and S. Arya and Parvathy, \{S. J.\} and Vulligaddala, \{Veeresh Babu\}",

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Rahul, T, Sahoo, B, Arya, S, Parvathy, SJ & Vulligaddala, VB 2015, A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application. in Proceedings of the 28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems. February edn, 7031744, Proceedings of the IEEE International Conference on VLSI Design, no. February, vol. 2015-February, IEEE Computer Society, pp. 265-270, 28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems, Bangalore, India, 01/3/15. https://doi.org/10.1109/VLSID.2015.51

A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application. / Rahul, T.; Sahoo, Bibhudatta; Arya, S. et al.
Proceedings of the 28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems. February. ed. IEEE Computer Society, 2015. p. 265-270 7031744 (Proceedings of the IEEE International Conference on VLSI Design; Vol. 2015-February, No. February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application

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AU - Sahoo, Bibhudatta

AU - Arya, S.

AU - Parvathy, S. J.

AU - Vulligaddala, Veeresh Babu

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N2 - This paper proposes a wide dynamic-range low-power signal conditioning circuit for low-side current sensing application. The proposed architecture uses a double sampling technique for switched capacitor programmable gain amplifier (SC-PGA) thus enabling the PGA to work at low frequency. However, the analog-to-digital converter (ADC), which digitizes the amplified signal works at high frequency to achieve high dynamic range. The double sampling technique relaxes the slew rate and settling requirement of the op amp in the PGA. The switched capacitor implementation obviates the need for explicit level-shifting circuit while enabling rail-to-rail input common mode. The closed loop SC-PGA architecture is very robust to gain drift due to temperature and supply voltage variation. The design incorporates correlated double sampling technique to overcome offset and flicker noise. The analog-to-digital converter used in this design is a multi-bit second order ΔΣ-ADC [14]. The circuit is implemented in AMS 0.35 μm CMOS process with 3.3 V supply. Simulations show that the overall system, i.e., PGA and ΔΣ-ADC, achieves a dynamic range in excess of 80 dB while consuming 2 mA.

AB - This paper proposes a wide dynamic-range low-power signal conditioning circuit for low-side current sensing application. The proposed architecture uses a double sampling technique for switched capacitor programmable gain amplifier (SC-PGA) thus enabling the PGA to work at low frequency. However, the analog-to-digital converter (ADC), which digitizes the amplified signal works at high frequency to achieve high dynamic range. The double sampling technique relaxes the slew rate and settling requirement of the op amp in the PGA. The switched capacitor implementation obviates the need for explicit level-shifting circuit while enabling rail-to-rail input common mode. The closed loop SC-PGA architecture is very robust to gain drift due to temperature and supply voltage variation. The design incorporates correlated double sampling technique to overcome offset and flicker noise. The analog-to-digital converter used in this design is a multi-bit second order ΔΣ-ADC [14]. The circuit is implemented in AMS 0.35 μm CMOS process with 3.3 V supply. Simulations show that the overall system, i.e., PGA and ΔΣ-ADC, achieves a dynamic range in excess of 80 dB while consuming 2 mA.

KW - double sampling

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KW - PGA

KW - second-order ΔΣADC

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BT - Proceedings of the 28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems

PB - IEEE Computer Society

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Rahul T, Sahoo B, Arya S, Parvathy SJ, Vulligaddala VB. A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application. In Proceedings of the 28th International Conference on VLSI Design, VLSID 2015 - held concurrently with the 14th International Conference on Embedded Systems. February ed. IEEE Computer Society. 2015. p. 265-270. 7031744. (Proceedings of the IEEE International Conference on VLSI Design; February). doi: 10.1109/VLSID.2015.51

A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application

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