A pick-and-place process control based on the bootstrapping method for quality enhancement in surface mount technology

The electronics manufacturing industry has undergone a transition towards lead-free processes and miniaturization; these changes require advancements in assembly techniques. Recent studies have identified that solder paste misalignment leads to larger component shifting, particularly observed with small passive components, resulting in more frequent quality rejections based on Institute of Printed Circuits standards. To address these challenges, various placement methods have been introduced. Among these, the AI-based mounter optimization module emerges as a leading approach, leveraging advanced machine learning methods to optimize component placement. However, it requires a substantial design of experiments and intentionally applies solder paste and chip placement offsets, which can lead to lower assembly quality, increased rework, or higher scrap rates. This paper proposes a placement method that collects real-time data from all inspection machines and positions a component considering the displacement occurring during the reflow process to reduce component misalignment after soldering. The proposed method utilizes a statistical approach by estimating the upper and lower confidence intervals for the average self-alignment degree and updates the chip placing location without requiring the design of experiments. The purpose of this study is to develop a placement method that enhances assembly quality, such as side overhang and end overlap, under solder paste misalignment. The proposed method is compared with the industry-standard placement method to demonstrate its effectiveness in improving assembly quality.