A novel VLSI divide and conquer array architecture for Vector-Scalar multiplication

Thomas Poonnen; Adly T. Fam

doi:10.1109/ICICDT.2007.4299540

A novel VLSI divide and conquer array architecture for Vector-Scalar multiplication

Thomas Poonnen
, Adly T. Fam

Department of Electrical Engineering

SUNY Buffalo
Panavision Imaging, LLC

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A novel VLSI array architecture for vector-scalar multiplication is introduced. It is based on a parameterized divide and conquer algorithm that uses optimal partitioning and redundancy removal for simultaneous computation of partial sums. Two variations of the proposed Parameterized Vector-Scalar Multiplier Architecture (PVSMA), namely PVSMA-A and PVSMA-AT, are implemented and compared to the parallel implementation with carry-save array multipliers. PVSMA-A is optimized for area (A), and is shown to achieve significant area (A) savings at the cost of increased operational delay (T). PVSMA-AT is optimized for area-time product (AT), and is shown to achieve significant area-time product (AT) savings and a smaller operational delay (T) at the cost of smaller area (A) savings.

Original language	English
Title of host publication	Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT
Pages	41-44
Number of pages	4
DOIs	https://doi.org/10.1109/ICICDT.2007.4299540
State	Published - 2007
Event	2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT - Austin, TX, United States Duration: May 30 2007 → Jun 1 2007

Publication series

Name	Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Conference

Conference	2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT
Country/Territory	United States
City	Austin, TX
Period	05/30/07 → 06/1/07

Keywords

Array architecture
Parameterized divide and conquer algorithm
Vector-scalar multiplication
Very large scale integration

Access to Document

10.1109/ICICDT.2007.4299540

Cite this

Poonnen, T., & Fam, A. T. (2007). A novel VLSI divide and conquer array architecture for Vector-Scalar multiplication. In Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT (pp. 41-44). Article 4299540 (Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT). https://doi.org/10.1109/ICICDT.2007.4299540

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title = "A novel VLSI divide and conquer array architecture for Vector-Scalar multiplication",

abstract = "A novel VLSI array architecture for vector-scalar multiplication is introduced. It is based on a parameterized divide and conquer algorithm that uses optimal partitioning and redundancy removal for simultaneous computation of partial sums. Two variations of the proposed Parameterized Vector-Scalar Multiplier Architecture (PVSMA), namely PVSMA-A and PVSMA-AT, are implemented and compared to the parallel implementation with carry-save array multipliers. PVSMA-A is optimized for area (A), and is shown to achieve significant area (A) savings at the cost of increased operational delay (T). PVSMA-AT is optimized for area-time product (AT), and is shown to achieve significant area-time product (AT) savings and a smaller operational delay (T) at the cost of smaller area (A) savings.",

keywords = "Array architecture, Parameterized divide and conquer algorithm, Vector-scalar multiplication, Very large scale integration",

author = "Thomas Poonnen and Fam, \{Adly T.\}",

year = "2007",

doi = "10.1109/ICICDT.2007.4299540",

language = "English",

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series = "Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT",

pages = "41--44",

booktitle = "Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT",

note = "2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT ; Conference date: 30-05-2007 Through 01-06-2007",

}

Poonnen, T & Fam, AT 2007, A novel VLSI divide and conquer array architecture for Vector-Scalar multiplication. in Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT., 4299540, Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT, pp. 41-44, 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT, Austin, TX, United States, 05/30/07. https://doi.org/10.1109/ICICDT.2007.4299540

A novel VLSI divide and conquer array architecture for Vector-Scalar multiplication. / Poonnen, Thomas; Fam, Adly T.
Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT. 2007. p. 41-44 4299540 (Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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A novel VLSI divide and conquer array architecture for Vector-Scalar multiplication

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Keywords

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