A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy

Yung Yuan Chen; Shambhu J. Upadhyaya

doi:10.1109/DFTVS.1991.199957

A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy

Yung Yuan Chen
, Shambhu J. Upadhyaya

Department of Computer Science and Engineering

SUNY Buffalo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The on-chip redundancy left unused in a fault tolerant system after successfully reconfiguring and eliminating the manufacturing defects is called residual redundancy. This redundancy can be used to improve the operational reliability of the system. We present a new hierarchical model to analyze the effect of residual redundancy on performance improvement of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy. Our model emphasizes the effect of support circuit (interconnection) failures on system reliability, a practical issue of great concern in WSI technology. Results of a simulation conducted to validate our model are discussed.

Original language	English
Title of host publication	1991 Proceedings - IEEE International Workshop on Defect and Fault Tolerance on VLSI Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	157-160
Number of pages	4
ISBN (Electronic)	0818624574
DOIs	https://doi.org/10.1109/DFTVS.1991.199957
State	Published - 1991
Event	1991 IEEE International Workshop on Defect and Fault Tolerance on VLSI Systems, DFT 1991 - Hidden Valley, United States Duration: Nov 18 1991 → Nov 20 1991

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Volume	1991-November
ISSN (Print)	1550-5774

Conference

Conference	1991 IEEE International Workshop on Defect and Fault Tolerance on VLSI Systems, DFT 1991
Country/Territory	United States
City	Hidden Valley
Period	11/18/91 → 11/20/91

Access to Document

10.1109/DFTVS.1991.199957

Cite this

Chen, Y. Y., & Upadhyaya, S. J. (1991). A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy. In 1991 Proceedings - IEEE International Workshop on Defect and Fault Tolerance on VLSI Systems (pp. 157-160). Article 199957 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems; Vol. 1991-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFTVS.1991.199957

Chen, Yung Yuan ; Upadhyaya, Shambhu J. / A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy. 1991 Proceedings - IEEE International Workshop on Defect and Fault Tolerance on VLSI Systems. Institute of Electrical and Electronics Engineers Inc., 1991. pp. 157-160 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

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title = "A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy",

abstract = "The on-chip redundancy left unused in a fault tolerant system after successfully reconfiguring and eliminating the manufacturing defects is called residual redundancy. This redundancy can be used to improve the operational reliability of the system. We present a new hierarchical model to analyze the effect of residual redundancy on performance improvement of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy. Our model emphasizes the effect of support circuit (interconnection) failures on system reliability, a practical issue of great concern in WSI technology. Results of a simulation conducted to validate our model are discussed.",

author = "Chen, \{Yung Yuan\} and Upadhyaya, \{Shambhu J.\}",

note = "Publisher Copyright: {\textcopyright} 1991 IEEE.; 1991 IEEE International Workshop on Defect and Fault Tolerance on VLSI Systems, DFT 1991 ; Conference date: 18-11-1991 Through 20-11-1991",

year = "1991",

doi = "10.1109/DFTVS.1991.199957",

language = "English",

series = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "157--160",

booktitle = "1991 Proceedings - IEEE International Workshop on Defect and Fault Tolerance on VLSI Systems",

address = "United States",

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Chen, YY & Upadhyaya, SJ 1991, A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy. in 1991 Proceedings - IEEE International Workshop on Defect and Fault Tolerance on VLSI Systems., 199957, Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, vol. 1991-November, Institute of Electrical and Electronics Engineers Inc., pp. 157-160, 1991 IEEE International Workshop on Defect and Fault Tolerance on VLSI Systems, DFT 1991, Hidden Valley, United States, 11/18/91. https://doi.org/10.1109/DFTVS.1991.199957

A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy. / Chen, Yung Yuan; Upadhyaya, Shambhu J.
1991 Proceedings - IEEE International Workshop on Defect and Fault Tolerance on VLSI Systems. Institute of Electrical and Electronics Engineers Inc., 1991. p. 157-160 199957 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems; Vol. 1991-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - The on-chip redundancy left unused in a fault tolerant system after successfully reconfiguring and eliminating the manufacturing defects is called residual redundancy. This redundancy can be used to improve the operational reliability of the system. We present a new hierarchical model to analyze the effect of residual redundancy on performance improvement of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy. Our model emphasizes the effect of support circuit (interconnection) failures on system reliability, a practical issue of great concern in WSI technology. Results of a simulation conducted to validate our model are discussed.

AB - The on-chip redundancy left unused in a fault tolerant system after successfully reconfiguring and eliminating the manufacturing defects is called residual redundancy. This redundancy can be used to improve the operational reliability of the system. We present a new hierarchical model to analyze the effect of residual redundancy on performance improvement of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy. Our model emphasizes the effect of support circuit (interconnection) failures on system reliability, a practical issue of great concern in WSI technology. Results of a simulation conducted to validate our model are discussed.

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DO - 10.1109/DFTVS.1991.199957

M3 - Conference contribution

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BT - 1991 Proceedings - IEEE International Workshop on Defect and Fault Tolerance on VLSI Systems

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Chen YY, Upadhyaya SJ. A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy. In 1991 Proceedings - IEEE International Workshop on Defect and Fault Tolerance on VLSI Systems. Institute of Electrical and Electronics Engineers Inc. 1991. p. 157-160. 199957. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). doi: 10.1109/DFTVS.1991.199957

A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy

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