TY - GEN
T1 - A multi-pole single-tap IIR based DFE equalizer topology
AU - Jacob, Nevin Alex
AU - Choudhary, Vikas
AU - Sahoo, Bibhudatta
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/10/22
Y1 - 2014/10/22
N2 - Decision feedback equalizer (DFE) using finite impulse response (FIR) feedback filter forms the backbone of modern wireline communication receivers. Incorporating infinite impulse response (IIR) feedback filtering in DFE is an upcoming area of research owing to the inherent power efficiency of analog filtering. Till date, multiple pole IIR based DFEs have been primarily implemented using multiple, single-pole IIR filters. In this paper, we propose a new architecture that can replace multiple single-pole IIR filters with a single IIR which has multiple poles, thus saving area and power compared to its predecessors. The proposed architecture can be tuned for existing wireline channels whose pulse-responses are characterized by long tails. Simulations of the proposed architecture in 65-nm UMC65-SP show more than 50% improvement in eye height and more than 25% improvement in timing jitter for cascaded B12 and cascaded T12 channels at 8-Gbps.
AB - Decision feedback equalizer (DFE) using finite impulse response (FIR) feedback filter forms the backbone of modern wireline communication receivers. Incorporating infinite impulse response (IIR) feedback filtering in DFE is an upcoming area of research owing to the inherent power efficiency of analog filtering. Till date, multiple pole IIR based DFEs have been primarily implemented using multiple, single-pole IIR filters. In this paper, we propose a new architecture that can replace multiple single-pole IIR filters with a single IIR which has multiple poles, thus saving area and power compared to its predecessors. The proposed architecture can be tuned for existing wireline channels whose pulse-responses are characterized by long tails. Simulations of the proposed architecture in 65-nm UMC65-SP show more than 50% improvement in eye height and more than 25% improvement in timing jitter for cascaded B12 and cascaded T12 channels at 8-Gbps.
UR - https://www.scopus.com/pages/publications/84914704592
U2 - 10.1109/NEWCAS.2014.6933970
DO - 10.1109/NEWCAS.2014.6933970
M3 - Conference contribution
AN - SCOPUS:84914704592
T3 - 2014 IEEE 12th International New Circuits and Systems Conference, NEWCAS 2014
SP - 1
EP - 4
BT - 2014 IEEE 12th International New Circuits and Systems Conference, NEWCAS 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 12th IEEE International New Circuits and Systems Conference, NEWCAS 2014
Y2 - 22 June 2014 through 25 June 2014
ER -