@inproceedings{35fbf06084e443c28b8d672f74c3da97,
title = "A Low Power Cyclic ADC Architecture using Reference Scaling Technique",
abstract = "This paper presents a prototype 9-bit 10MS/s cyclic Analog-to-Digital Converter (ADC) with reference scaling technique. The idea of reference scaling in cyclic ADC has yet to be explored, even though it has been used in pipelined ADC. The proposed ADC has two sub-ADC blocks along with two MDAC sampling networks and an OTA, which is shared between the two MDAC sampling networks in every alternative clock period. During the first bit-cycling phase, voltage swing is reduced, and reference voltages are scaled down by the same factor for the subsequent bit-cycling phases. A proof-of-concept ADC is designed and simulated in 65nm CMOS technology. This ADC achieves an SNDR of 52.5 dB and SFDR of 57.1 dB with a 1.2V peak-to-peak sinusoidal input signal of frequency 5MHz sampled at 10MHz while consuming 260μW power from 1.2V supply.",
keywords = "1.5-bit architecture, Cyclic ADC, reference scaling, switched-capacitor",
author = "Kousik Das and Senorita Deb and Sahoo, \{Bibhu Datta\}",
note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 ; Conference date: 21-05-2023 Through 25-05-2023",
year = "2023",
doi = "10.1109/ISCAS46773.2023.10181698",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings",
address = "United States",
}