A low-power current-mode clock distribution scheme for multi-GHz NoC-based SoCs

Ashok Narasimhan; Shantanu Divekar; Praveen Elakkumanan; Ramalingam Sridhar

doi:10.1109/ICVD.2005.18

A low-power current-mode clock distribution scheme for multi-GHz NoC-based SoCs

Ashok Narasimhan
, Shantanu Divekar
, Praveen Elakkumanan
, Ramalingam Sridhar

Department of Computer Science and Engineering

SUNY Buffalo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

13 Scopus citations

Abstract

Performance of System-on-Chips (SoC) is limited by rising delays and noise in buses and point-to-point interconnects. This also has a profound impact on the clock distribution network. Networks-on-Chip (NoC) provides a regular communication fabric that helps to overcome these limitations. However, NoCs too will face bottlenecks in clocking beyond a few GHz in voltage mode clock signaling. This work presents a reliable quasi-synchronous clock distribution scheme for NoCs that uses a single-ended current-mode clock signaling technique. Simulation results show the circuit to be reliable under process variations, and having an average of 11% improvement in delay and average power over other current mode schemes. Simulation results indicate acceptable performance up to 7.5GHz in 0.18μm technology.

Original language	English
Title of host publication	Proceedings of the 18th International Conference on VLSI Design
Pages	130-133
Number of pages	4
DOIs	https://doi.org/10.1109/ICVD.2005.18
State	Published - 2005
Event	18th International Conference on VLSI Design: Power Aware Design of VLSI Systems - Kolkata, India Duration: Jan 3 2005 → Jan 7 2005

Publication series

Name	Proceedings of the IEEE International Conference on VLSI Design
ISSN (Print)	1063-9667

Conference

Conference	18th International Conference on VLSI Design: Power Aware Design of VLSI Systems
Country/Territory	India
City	Kolkata
Period	01/3/05 → 01/7/05

Access to Document

10.1109/ICVD.2005.18

Cite this

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title = "A low-power current-mode clock distribution scheme for multi-GHz NoC-based SoCs",

abstract = "Performance of System-on-Chips (SoC) is limited by rising delays and noise in buses and point-to-point interconnects. This also has a profound impact on the clock distribution network. Networks-on-Chip (NoC) provides a regular communication fabric that helps to overcome these limitations. However, NoCs too will face bottlenecks in clocking beyond a few GHz in voltage mode clock signaling. This work presents a reliable quasi-synchronous clock distribution scheme for NoCs that uses a single-ended current-mode clock signaling technique. Simulation results show the circuit to be reliable under process variations, and having an average of 11\% improvement in delay and average power over other current mode schemes. Simulation results indicate acceptable performance up to 7.5GHz in 0.18μm technology.",

author = "Ashok Narasimhan and Shantanu Divekar and Praveen Elakkumanan and Ramalingam Sridhar",

year = "2005",

doi = "10.1109/ICVD.2005.18",

language = "English",

isbn = "0769522645",

series = "Proceedings of the IEEE International Conference on VLSI Design",

pages = "130--133",

booktitle = "Proceedings of the 18th International Conference on VLSI Design",

note = "18th International Conference on VLSI Design: Power Aware Design of VLSI Systems ; Conference date: 03-01-2005 Through 07-01-2005",

}

Narasimhan, A, Divekar, S, Elakkumanan, P & Sridhar, R 2005, A low-power current-mode clock distribution scheme for multi-GHz NoC-based SoCs. in Proceedings of the 18th International Conference on VLSI Design. Proceedings of the IEEE International Conference on VLSI Design, pp. 130-133, 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems, Kolkata, India, 01/3/05. https://doi.org/10.1109/ICVD.2005.18

A low-power current-mode clock distribution scheme for multi-GHz NoC-based SoCs. / Narasimhan, Ashok; Divekar, Shantanu; Elakkumanan, Praveen et al.
Proceedings of the 18th International Conference on VLSI Design. 2005. p. 130-133 (Proceedings of the IEEE International Conference on VLSI Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A low-power current-mode clock distribution scheme for multi-GHz NoC-based SoCs

AU - Narasimhan, Ashok

AU - Divekar, Shantanu

AU - Elakkumanan, Praveen

AU - Sridhar, Ramalingam

PY - 2005

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N2 - Performance of System-on-Chips (SoC) is limited by rising delays and noise in buses and point-to-point interconnects. This also has a profound impact on the clock distribution network. Networks-on-Chip (NoC) provides a regular communication fabric that helps to overcome these limitations. However, NoCs too will face bottlenecks in clocking beyond a few GHz in voltage mode clock signaling. This work presents a reliable quasi-synchronous clock distribution scheme for NoCs that uses a single-ended current-mode clock signaling technique. Simulation results show the circuit to be reliable under process variations, and having an average of 11% improvement in delay and average power over other current mode schemes. Simulation results indicate acceptable performance up to 7.5GHz in 0.18μm technology.

AB - Performance of System-on-Chips (SoC) is limited by rising delays and noise in buses and point-to-point interconnects. This also has a profound impact on the clock distribution network. Networks-on-Chip (NoC) provides a regular communication fabric that helps to overcome these limitations. However, NoCs too will face bottlenecks in clocking beyond a few GHz in voltage mode clock signaling. This work presents a reliable quasi-synchronous clock distribution scheme for NoCs that uses a single-ended current-mode clock signaling technique. Simulation results show the circuit to be reliable under process variations, and having an average of 11% improvement in delay and average power over other current mode schemes. Simulation results indicate acceptable performance up to 7.5GHz in 0.18μm technology.

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BT - Proceedings of the 18th International Conference on VLSI Design

T2 - 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems

Y2 - 3 January 2005 through 7 January 2005

ER -

A low-power current-mode clock distribution scheme for multi-GHz NoC-based SoCs

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