TY - GEN
T1 - A low-power asymmetric source driver level converter based current-mode signaling scheme for global interconnects
AU - Narasimhan, Ashok
AU - Srinivasaraghavan, Bhooma
AU - Sridhar, Ramalingam
PY - 2006
Y1 - 2006
N2 - Global interconnects pose a significant challenge to the dense Very Deep Submicron (VDSM) System-on-Chips (SoC), due to increasing wire delay and its variations. Hence, interconnection techniques which decrease delay, delay variation and ensure signal integrity, play an important role in future technologies. In this regard, current-mode low-swing interconnection techniques provide an attractive alternative to conventional full-swing voltage-mode techniques in terms of delay, power and noise immunity. In this paper, we present a new current-mode low swing interconnection technique that reduces the delay and delay variations in global interconnects. Simulation results indicate significant savings in power, reduction in delay and increase in noise immunity compared to other techniques.
AB - Global interconnects pose a significant challenge to the dense Very Deep Submicron (VDSM) System-on-Chips (SoC), due to increasing wire delay and its variations. Hence, interconnection techniques which decrease delay, delay variation and ensure signal integrity, play an important role in future technologies. In this regard, current-mode low-swing interconnection techniques provide an attractive alternative to conventional full-swing voltage-mode techniques in terms of delay, power and noise immunity. In this paper, we present a new current-mode low swing interconnection technique that reduces the delay and delay variations in global interconnects. Simulation results indicate significant savings in power, reduction in delay and increase in noise immunity compared to other techniques.
UR - https://www.scopus.com/pages/publications/33748524869
U2 - 10.1109/VLSID.2006.16
DO - 10.1109/VLSID.2006.16
M3 - Conference contribution
AN - SCOPUS:33748524869
SN - 0769525024
SN - 9780769525020
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 491
EP - 494
BT - Proceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
T2 - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Y2 - 3 January 2006 through 7 January 2006
ER -