A low power and low area active clock deskewing technique for sub-90nm technologies

Unintentional clock skew caused by variability can result in degraded and unreliable system performance. In this paper, we present a deskewing technique that continuously senses and compensates for unintentional clock skew. It uses an enhanced skew detector block that detects the skew magnitude in addition to the phase. This helps eliminate the need for complex feedback control, thus reducing the power consumption and the area overhead. Simulation results on a benchmark circuit in 65nm technology show that the deskewed clock has less than 1ps skew at clock frequencies of upto 2.5GHz and 55ps of input skew. Power consumed and area overhead in the deskew circuit is reduced by greater than 50% and 40% respectively, compared to other techniques. Montecarlo simulation of process variations shows maximum output skew of less than 18ps, and a standard deviation of 1mW in power consumed in the deskewing circuit.