A high throughput router with a novel switch allocator for network on chip

As industry moves towards many core chips, conventional bus and crossbar interconnections often struggle to meet the multi-core communication requirement. Network on Chip (NoC) has been proposed to replace global interconnections to alleviate this problem. In NoC, routers are used to exchange data between IPs. So the router performance directly impacts the efficiency of the entire system. The key components of a modern router include Route Computation (RC), Virtual-channel Allocation (VA), Switch Allocation (SA) and Switch Traversal (ST). In this paper, we present a new router architecture that significantly improves the throughput while keeping the area overhead low. In this approach, we redesign SA's fist stage arbiters to be priority based dynamic arbiters using round-robin algorithm. The modified unit can increase the possibility of SA's first stage arbiters to choose requests for different output ports. Hence, in the second stage of the SA, the competition for output ports will be reduced, leading more flits to travel through the crossbar in one cycle, resulting in increased throughput. Our results show that the new design can improve throughput by up to 13% for a router with eight virtual channels. Also, the new arbiter has lower worst case latency which can help the system to increase its operational frequency.