A high-performance router design for VDSM NoCs

The rising interconnect delay and delay variations pose significant communication challenges in deep submicron System-on-Chips. Interconnect-centric design methodologies such as Network-on-Chip have been proposed as potential solutions to overcome these challenges. In this paper, we present the design of an NoC router that achieves high performance by increasing the network resource utilization, while still supporting both Guaranteed Bandwidth and Best Effort services. Simulation results indicate low jitter and minimal variation in packet latencies under different traffic compositions, thus ensuring consistent high performance of the interconnect network and the NoC.