A half Dl MPEG-4 encoder on the BSP-15 DSP

Lulin Chen; Zhihai He; Chang Wen Chen; Michael Isnardi

doi:10.1117/12.538252

A half Dl MPEG-4 encoder on the BSP-15 DSP

Lulin Chen
, Zhihai He
, Chang Wen Chen
, Michael Isnardi

Department of Computer Science and Engineering

Sarnoff Corporation
University of Missouri

Research output: Contribution to journal › Conference article › peer-review

2 Scopus citations

Abstract

In this paper, we present the work on implementation of a half-Dl interlaced MPEG-4 encoder with Equator Technology DSP chip, BSP-15. The BSP-15 DSP consists mainly of a VLIW core, Co-processors, and media I/O interfaces. The encoder utilizes several BSP-15 functional blocks in parallel. In general, the VLIW performs pixel processing that is computationally intensive. The VLx coprocessor completes variable length coding. Further parallelism is obtained by pre-loading data cache and doubling data buffers. Given the DSP processing power and real time requirements, a complexity control scheme is implemented. A frame-level quantization scheme with quality and rate control is employed. The current implementation for video at 30 fps consumes about 90% of the chip performance at a bit rate ∼2Mbps.

Original language	English
Pages (from-to)	1-5
Number of pages	5
Journal	Proceedings of SPIE - The International Society for Optical Engineering
Volume	5308
Issue number	PART 1
DOIs	https://doi.org/10.1117/12.538252
State	Published - 2004
Event	Visual Communications and Image Processing 2004 - San Jose, CA, United States Duration: Jan 20 2004 → Jan 22 2004

Keywords

Compression
DSP
Optimization
Video

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10.1117/12.538252

Cite this

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title = "A half Dl MPEG-4 encoder on the BSP-15 DSP",

abstract = "In this paper, we present the work on implementation of a half-Dl interlaced MPEG-4 encoder with Equator Technology DSP chip, BSP-15. The BSP-15 DSP consists mainly of a VLIW core, Co-processors, and media I/O interfaces. The encoder utilizes several BSP-15 functional blocks in parallel. In general, the VLIW performs pixel processing that is computationally intensive. The VLx coprocessor completes variable length coding. Further parallelism is obtained by pre-loading data cache and doubling data buffers. Given the DSP processing power and real time requirements, a complexity control scheme is implemented. A frame-level quantization scheme with quality and rate control is employed. The current implementation for video at 30 fps consumes about 90\% of the chip performance at a bit rate ∼2Mbps.",

keywords = "Compression, DSP, Optimization, Video",

author = "Lulin Chen and Zhihai He and Chen, \{Chang Wen\} and Michael Isnardi",

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AU - Chen, Lulin

AU - He, Zhihai

AU - Chen, Chang Wen

AU - Isnardi, Michael

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N2 - In this paper, we present the work on implementation of a half-Dl interlaced MPEG-4 encoder with Equator Technology DSP chip, BSP-15. The BSP-15 DSP consists mainly of a VLIW core, Co-processors, and media I/O interfaces. The encoder utilizes several BSP-15 functional blocks in parallel. In general, the VLIW performs pixel processing that is computationally intensive. The VLx coprocessor completes variable length coding. Further parallelism is obtained by pre-loading data cache and doubling data buffers. Given the DSP processing power and real time requirements, a complexity control scheme is implemented. A frame-level quantization scheme with quality and rate control is employed. The current implementation for video at 30 fps consumes about 90% of the chip performance at a bit rate ∼2Mbps.

AB - In this paper, we present the work on implementation of a half-Dl interlaced MPEG-4 encoder with Equator Technology DSP chip, BSP-15. The BSP-15 DSP consists mainly of a VLIW core, Co-processors, and media I/O interfaces. The encoder utilizes several BSP-15 functional blocks in parallel. In general, the VLIW performs pixel processing that is computationally intensive. The VLx coprocessor completes variable length coding. Further parallelism is obtained by pre-loading data cache and doubling data buffers. Given the DSP processing power and real time requirements, a complexity control scheme is implemented. A frame-level quantization scheme with quality and rate control is employed. The current implementation for video at 30 fps consumes about 90% of the chip performance at a bit rate ∼2Mbps.

KW - Compression

KW - DSP

KW - Optimization

KW - Video

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DO - 10.1117/12.538252

M3 - Conference article

AN - SCOPUS:10444220138

SN - 0277-786X

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SP - 1

EP - 5

JO - Proceedings of SPIE - The International Society for Optical Engineering

JF - Proceedings of SPIE - The International Society for Optical Engineering

IS - PART 1

T2 - Visual Communications and Image Processing 2004

Y2 - 20 January 2004 through 22 January 2004

ER -

A half Dl MPEG-4 encoder on the BSP-15 DSP

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Keywords

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