A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology

This paper presents techniques for gate-oxide and middle-of-line (MOL) time-dependent dielectric breakdown (TDDB) lifetime assessment of microprocessors and digital circuits. Both traditional CMOS and the state-of-art FinFET technology are taken into consideration. A circuit's lifetime distribution depends on its usage and the resulting temperature profile. Emulation of the circuit operation extracts the relevant usage parameters. These parameters are converted to state probabilities at the inputs of the standard cells. The lifetime distributions of standard cells are characterized by taking into account all possible input state probabilities and die-to-die process variations. Because MOL TDDB depends on the layout, a step involved in estimating the lifetime distributions of standard cells is the analysis of the layout for MOL TDDB. Two different methods to extract the layout features are presented for traditional CMOS and FinFET technologies. By precharacterizing the standard cell lifetime distribution, our simulator can find the lifetime limiting cells in a circuit, and thus, circuit designers can replace such cells with a combination of standard cells with a longer lifetime to make the circuit more robust. The results also indicate that we need to pay more attention to the newly emerging MOL TDDB when designing new standard cells for FinFET technology.