TY - GEN
T1 - A comparison study of time-dependent dielectric breakdown for analog and digital circuit's optimal accelerated test regions
AU - Yang, Kexin
AU - Liu, Taizhi
AU - Zhang, Rui
AU - Milor, Linda
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/2
Y1 - 2017/7/2
N2 - This paper investigates not only the traditional reliability concern, frontend-of-line dielectric breakdown (GTDDB), but also the newly emerging wearout mechanism, Middle-of-Line (MOL) time dependent dielectric breakdown (MTDDB). The optimal accelerated test conditions for these mechanisms are presented, which involves separate test conditions for each mechanism. To perform circuit-level accelerated life test, the optimal conditions vary for analog and digital circuits and need to be carefully considered before conducting the tests. Only tests in the optimal region are able to reflect the lifetime of the target wearout mechanism. Circuit designers will benefit due to the fact that different test conditions detect different wearout mechanisms. Therefore, the accelerated tests will provide information on the causes of failure, and circuit designers can use this information to redesign their circuits in a more robust and reliable way.
AB - This paper investigates not only the traditional reliability concern, frontend-of-line dielectric breakdown (GTDDB), but also the newly emerging wearout mechanism, Middle-of-Line (MOL) time dependent dielectric breakdown (MTDDB). The optimal accelerated test conditions for these mechanisms are presented, which involves separate test conditions for each mechanism. To perform circuit-level accelerated life test, the optimal conditions vary for analog and digital circuits and need to be carefully considered before conducting the tests. Only tests in the optimal region are able to reflect the lifetime of the target wearout mechanism. Circuit designers will benefit due to the fact that different test conditions detect different wearout mechanisms. Therefore, the accelerated tests will provide information on the causes of failure, and circuit designers can use this information to redesign their circuits in a more robust and reliable way.
KW - digital circuit
KW - frontend-of-line dielectric breakdown
KW - lifetime
KW - middle-of-line breakdown
KW - radio-frequency circuit
KW - reliability
KW - time-dependent dielectric breakdown
KW - wearout
UR - https://www.scopus.com/pages/publications/85050806190
U2 - 10.1109/DCIS.2017.8311628
DO - 10.1109/DCIS.2017.8311628
M3 - Conference contribution
AN - SCOPUS:85050806190
T3 - 2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings
SP - 1
EP - 6
BT - 2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017
Y2 - 22 November 2017 through 24 November 2017
ER -