37 mS/μm In_0.53Ga_0.47as MOSFET with 5 nm channel and self-aligned epitaxial raised source/drain

InGaAs has been extensively studied as a potential channel material for sub-22nm gate length VLSI MOSFETs because of its low electron effective mass (m*) hence high electron velocity (v). At sub-22 nm gate lengths, a maximum 1 nm EOT dielectric and 5 nm thick channel with strong vertical confinement are required for high subthreshold slope and acceptably low drain induced barrier lowering (DIBL) [1, 2]. Most reported InGaAs MOSFETs [3, 4] have ≥ 10 nm channel thickness. The source/drain (S/D) junctions must be very shallow (∼5nm) with abrupt vertical and lateral profiles, yet extremely low (∼20ω-μm) source access resistance and consequently very low (∼0.3 ω-μm²) contact and (∼500ω) sheet resistivities are required to minimize degradation of the drive current (I _d) and transconductance g_m [1]. Such parameters are difficult to achieve in InGaAs by ion implantation of the N+ S/D, particularly if an InAlAs bottom confinement layer is used. S/D contacts must be self-aligned to the gate, yet there is no known equivalent of self-aligned silicides in III-V materials. Addressing these requirements, we had reported [5, 6] InGaAs MOSFETs with self-aligned S/D access regions and self-aligned metal contacts formed by MBE regrowth and in-situ metal deposition, though these showed low 0.02 mS/μ m transconductance. Here we report greatly improved devices with 0.37 mS/μm transconductance at 0.8 μm L_g.