1-Transistor-1-Memristor Multilevel Memory Cell

CMOS-hybrids with memristors is an upcoming memory technology with advantages like high-density, non-volatility, and low power consumption. Conventional memory applications and logic devices require the memristor to exhibit resistive switching threshold, while neuromorphic computing and analog applications require that the memristor be precisely tuned to a certain value. Memory density can be increased by realizing memory cells that can store more than 2 levels, i.e., multiple bits per cell. Realizing a multi-level memory cell using only one memristor falls into the category of analog application and hence, requires gradual resistance tuning (GRT). This paper proposes GRT based one-transistor-one-memristor (1T1M) multi-level memory cell. Designed and simulated in UMC 180nm technology with memristor modeled using VTEAM [7], an 8 Kbits memory is realized as a 64 × 64 memory array using the proposed 1T1M-memory cell (2-bits/cell). The proposed architecture has the advantages of zero-static power dissipation, low transient power consumption during read and write, and non-destructive read operations. The proposed 1T1M-memory cell can be extended to store more than 2-bits with high-accuracy sense amplifiers.